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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:12:47 04/25/2012 
-- Design Name: 
-- Module Name:    my_data_mux - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux is
	Port (
			data_in : in std_logic_vector(15 downto 0);
			index : in std_logic_vector(1 downto 0);
			data_out : out std_logic_vector(3 downto 0)
		);
end mux;

architecture Behavioral of mux is

begin

	with index select data_out <=
		data_in(3 downto 0) when "00",
		data_in(7 downto 4) when "01",
		data_in(11 downto 8) when "10",
		data_in(15 downto 12) when others;

end Behavioral;

